Successive approximation register (SAR) analog-to-digital converters (ADCs) typically resolve bits sequentially from most-significant bit (MSB) to least-significant bit (LSB) for each conversion. It can be a challenge to accurately determine the LSBs of a higher accuracy ADC (e.g., such as when the number of bits in the ADC is twelve or greater) and minimize conversion errors. The present inventors have recognized a need for SAR ADCs that are more robust and efficient for the bit trials performed during the conversion phase of the SAR ADCs.